AMD EPYC 7004 “Genoa” processor pictured, features twelve Zen4 chips

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AMD Epyc Genoa with 12 chips shown

Just yesterday, the first photo of the new SP5 (LGA6096) socket appeared, and now we can finally see the next-gen EPYC processor without the integrated heatsink.

A photo of a purported EPYC Genoa processor was shared on TF AMD (Top Talent) in Malaysia. This is the first photo showing the 12 chiplets installed on the SP5 package. What’s important to note here is that this is most likely a mockup and the photo is at least 10 months old (judging by when it was posted).

AMD EPYC “Genoa” processor, Source: AMD TF Malaysia/@Phatal187

EPYC Genoa offers up to 96 cores and 192 threads in its full configuration. AMD will release many SKUs with partially disabled cores, so just because this CPU has 12 chiplets doesn’t mean it will have all 96 cores active.

Each Zen4 CCD chip has an area of ​​72 mm², which is 8 mm² less than Zen3 (as on the EPYC “Milan” series). The I/O die is also smaller, around 397mm² compared to 416mm² on the Zen3 EPYC processors. That said, AMD had no trouble installing 6 chiplets on either side of the I/O die, given that the SP5 package (LGA 6096) is also 37% larger than the SP3.

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AMD EPYC “Genoa” processor, Source: AMD TF Malaysia/@Phatal187

AMD’s new SP5 platform will support up to 12 channels of DDR5 memory as well as the PCIe Gen5 interface. AMD Genoa is already shipping to early customers, according to AMD. The new EPYC 7004 series is now on track to launch by the end of this year.

Rumored AMD EPYC CPU Series Specs
video cardz 7001 “Naples” 7002 “Roma” 7003 “Milan”
7003 “Milan-X”
7004 “Genoa” 7004 “Bergamo”
7005 “Turin” To throw 2017 2019 2021 2022 2022
2023/2024 Architecture 14nm Zen 7nm Zen2 7nm Zen3 5nm Zen4 5nm Zen4c
Zen5 Plug SP3 (LGA4094) SP3 (LGA4094) SP3 (LGA4094) SP5 (LGA-6096) SP5 (LGA-6096)
SP5 (LGA-6096) Modules/Chips 4xCCD 8xCCD + 1xIOD 8xCCD + 1xIOD 12xCCD + 1xIOD 12xCCD + 1xIOD
To confirm
Maximum number of cores Maximum Clock To confirm To confirm
To confirm L2 cache per core 0.5 MB 0.5 MB 0.5 MB 1 MB To confirm
To confirm L3 cache by CCX 8 MB 8 MB 32MB / 96MB 32 MB
To confirm
To confirm
Memory channels Memory Support PCIe lanes
To confirm To confirm

Maximum cTDP To confirm Source: TF AMD Microelectronics



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